Hourra! les Tr 909 frôlent les 1000€

Vu la qualité médiocre des composants d'aujourd'hui par rapport à ceux d'antan, surement avant les 30 ans.

Un condo se change et tu devra surement changer les tiens aussi un jour.
Vu la qualité médiocre des composants d'aujourd'hui par rapport à ceux d'antan, surement avant les 30 ans.

Les sources sont multiples je te laisse aller faire des recherches sur les forums en électronique.

Les machines d'antan à la différence d'aujourd'hui étaient faites pour durer et non pour te forcer à la changer après quelques années.

The growth predicted by Moore’s Law has traditionally been achieved through “geometric
scaling”, associated with ongoing miniaturisation of selected technologies such as CMOS
transistors [300]. This is expected to continue for some aspects of chip manufacture [300].
Manufactured silicon MOSFET devices have been formally classed as nanotechnology (defined
as feature sizes less than 100 nanometres) since about the year 2000 [221]. The ability to
miniaturise further is increasingly being limited by concerns such as parasitic resistance and
parasitic capacitance, which were traditionally considered to be insignificant in scaling theories
[221]. As of early 2009, the state-of-the-art “node” for CMOS transistors was 45 nanometres,
which refers to the standard gate length for a single transistor [307]. As gate widths are scaled
further below 100 nanometres, classical laws of physics increasingly give way to quantum
DSTO-TR-2437
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mechanics, and CMOS devices become increasingly susceptible to quantum tunnelling effects
and thermal leakage currents, resulting in reduced performance [307].

Functional Diversification, also known as “More than Moore” (MtM), describes a longer-term
emerging trend, in which the semiconductor industry seeks to provide additional value to
customers in manners that don’t involve miniaturisation, such as support for non-digital
functionalities (RF communication, power control, increased usage of passive components,
sensors, or actuators) and increasing system level integration in chip, circuits, and system
packages associated with evolution to package-level (SiP), chip-level (SoC), and Stacked Chip
SoC (SCS) solutions [300]. It is forecast that capabilities offered by CMOS transistor processes
will need augmentation by integrating multiple new devices, at either chip or package level,
around a CMOS core [300]. MtM results in a number of technology and material challenges due
to trends towards higher interconnect densities in packages, increasing thermal densities,
increased challenges gaining access to test components within a package, and increasing
challenges of ensuring reliability

Je t'ai donné des sources, des citations et des pages qui appuient ce que j'ai dis.

Encore faut il les lire.